8-bit Up/Down Counter not working

i tried to write a code for an 8 bit up/down counter with active high synchronous reset using an always block , i have to use the nexys3 board to display the Q values on the first three 7 seg display with 0.7 second delay between two different values, the code did not have any errors, i assigned the pins and tried it on the board but didnt work at all .

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module UpDownCounter(Clock, Reset, Mode, Seg1, Seg2, Seg3, AN0, AN1, AN2);

input Clock, Reset, Mode;
output [6:0] Seg1, Seg2, Seg3;
output reg AN0, AN1,AN2;

wire NewClock;
wire [7:0] Q;
wire [3:0] Third, Second, First;

reg [25:0] DelayCounter;
reg [1:0] DisplayEnable;
reg [1:0] State;
parameter Delay = 50000000;

Clockdev ClkDev(.Clock(Clock), .Reset(Reset), .NewClock(NewClock));

Counter counter(.Clock(NewClock), .Reset(Reset), .Mode(Mode), .Q(Q));

BinaryToBCD BCD(.Binary(Q), .First(First), .Second(Second), .Third(Third));

SevenSeg DisThird(.Digit(Third), .Seg(Seg1));
SevenSeg DisSecond(.Digit(Second), .Seg(Seg2));
SevenSeg DisFirst(.Digit(First), .Seg(Seg3));

always @(posedge Clock or posedge Reset) begin
if (Reset) begin
AN0 <= 1; // Enable first display, disable others
AN1 <= 0;
AN2 <= 0;
end else begin
case(State)
2'b00: begin
AN0 <= 1; // Enable first 7-segment
AN1 <= 0;
AN2 <= 0;
end
2'b01: begin
AN0 <= 0;
AN1 <= 1; // Enable second 7-segment
AN2 <= 0;
end
2'b10: begin
AN0 <= 0;
AN1 <= 0;
AN2 <= 1; // Enable third 7-segment
end
default: begin
AN0 <= 0;
AN1 <= 0;
AN2 <= 0;
end
endcase
end
end
endmodule

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module Clockdev(Clock, Reset, NewClock);

input Clock, Reset;
output reg NewClock;
reg [27:0] Q=0;

always @(posedge Clock or posedge Reset) begin
if (Reset) begin
Q <= 0;
NewClock <= 0;
end else if (Q == 70000000) begin
Q <= 0;
NewClock <= ~NewClock;
end else begin
Q <= Q+1;
end
end

endmodule

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module Counter(Clock, Reset, Mode, Q);

input Clock, Reset, Mode;
output reg [8:0] Q;

always @(posedge Clock) begin
if (Reset == 1)
Q <= 8'b00000000;
else if (Mode == 1) begin
if (Q == 8'b11111111)
Q <= 8'b00000000;
else
Q <= Q+1;
end else begin
if (Q == 8'b00000000)
Q <= 8'b11111111;
else
Q <= Q-1;
end
end

endmodule

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module BinaryToBCD(Binary, First, Second, Third);

input [7:0] Binary;
output reg [3:0] First, Second, Third;

integer Temp;

always @(*) begin
Temp = Binary;
Third = Temp/100;
Temp = Temp%100;
Second = Temp/10;
First = Temp%10;
end

endmodule

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module SevenSeg(Digit, Seg);

input [3:0] Digit;
output reg [6:0] Seg;

always @(*) begin
case(Digit)
4'b0000: Seg = 7'b1000000;
4'b0001: Seg = 7'b1111001;
4'b0010: Seg = 7'b0100100;
4'b0011: Seg = 7'b0110000;
4'b0100: Seg = 7'b0011001;
4'b0101: Seg = 7'b0010010;
4'b0110: Seg = 7'b0000010;
4'b0111: Seg = 7'b1111000;
4'b1000: Seg = 7'b0000000;
4'b1001: Seg = 7'b0010000;
default: Seg = 7'b1111111;
endcase
end

endmodule